The invention relates to a structure and a method for protecting an integrated circuit against internal circuit damages caused by electrostatic discharge (ESD) and, in particular, to a structure and method for controlling the trigger voltage of the ESD protection devices.
Electrostatic discharge (ESD) is a well-known concern when designing an integrated circuit (IC). ESD events can occur at the input/output pads of an IC or the power supply pins. The ESD spikes can reach up to several thousand volts and can destroy circuitry within an IC, such as field effect transistors (FETs). Accordingly, integrated circuits frequently include some kind of protection circuit for preventing high voltage ESD spikes applied to input/output pads from reaching internal circuitry and causing permanent damages.
Conventional ESD protection devices rely on one or more p-n junction diodes to trigger an associated parasitic bipolar transistor connected to the input/output pad to shunt the ESD spikes to either the supply voltage Vdd pin or the ground pin. FIG. 1 is a cross-sectional view of a conventional ESD protection device 10 connected to a pad of an integrated circuit. Referring to FIG. 1, an input pad 12, besides being connected to the intended internal circuit element (not shown), is connected to an n+ diffusion 14 forming the cathode of a protection diode. A P-well 16 forms the anode of the protection diode and is connected to the ground voltage through p+ diffusion 18. A parasitic bipolar transistor, including n+ collector 14, p-base 16 and n+ emitter 19, is also formed between pad 12 and the ground voltage. ESD protection is afforded by the junction breakdown of the diode (n+ diffusion 14 and P-well 16) and the bipolar transistor action.
The voltage at which an ESD protection device is activated is referred to as the trigger voltage. In the ESD protection device of FIG. 1, the trigger voltage is determined by the reverse-biased breakdown voltage of the n+ (14) to P-well (16) junction and the inherent parasitic resistance of the p-n junction. To provide effective ESD protection, the protection device must be triggered before the ESD voltage reaches the protected device, causing the protected device to break down and self-destruct.
As technology is scaled for smaller feature sizes, the breakdown voltage of semiconductor devices decreases. The smaller breakdown voltage reduces the voltage margin between the breakdown voltage of semiconductor devices to be protected and the trigger voltage of the ESD protection devices. Due to the inherent parasitic resistance of the ESD protection device, the trigger voltage can actually exceed the breakdown voltage of the protected device, rendering the ESD protection device useless. Prior art techniques for reducing the parasitic resistance, and thereby the trigger voltage, of the ESD protection device are unsatisfactory because these techniques generally involve increasing the layout area of the protection device.
Therefore, it is desirable to provide effective ESD protection as technology scales down without increasing the size of the ESD protection device.
According to one embodiment of the present invention, a semiconductor device formed in a semiconductor substrate for protecting against electrostatic discharge includes a first region of a first conductivity type and having a first dopant concentration. The first region is coupled to an input pad of an integrated circuit. The semiconductor device further includes a first well of a second conductivity type where the first well extending partially under the first region, a second region of the second conductivity type formed in the first well and having a dopant concentration greater than a dopant concentration of the first well, and a third region of the first conductivity type formed in the second region and being connected to a reference voltage. The third region has a dopant concentration greater than the dopant concentration of the second region. Finally, the semiconductor device includes a fourth region of the second conductivity type formed in the second region and being connected to the reference voltage. The fourth region has a dopant concentration greater than the dopant concentration of the second region.
In the semiconductor device, the first region and the first well forms the p-n junction of a trigger diode, and the first region forms a collector region, the first well and the second region form a base and the third region forms an emitter region of an NPN transistor. The incorporation of the second region encourages bulk transistor action and inhibits surface transistor action such that the reliability of the semiconductor device is enhanced.
According to another aspect of the present invention, a diode-triggered bipolar transistor ESD protection device includes a diode having a junction of a p-type semiconductor material and an n-type semiconductor material where the junction of the diode has a shaped periphery. The anode of the diode is coupled to a reference voltage and the cathode of the diode is coupled to a pad of an integrated circuit. The ESD protection device also includes a transistor having a first current handling terminal coupled to the pad, a second current handling terminal coupled to the reference voltage, and a control terminal coupled to the anode of the diode. In operation, the diode provides reverse-biased breakdown current to the transistor when a voltage at the pad exceeds a breakdown voltage of the diode.
The shaped periphery of the junction can include a corrugated boundary, a perforated boundary and other shapes for extending the length of the junction periphery.
In other embodiments, the ESD protection device can be a diode-triggered SCR type ESD protection device, such as an N+/P-Well triggered SCR type ESD protection device or an LVTSCR type ESD protection device.